FIFOs are often used in systems to store data on a temporary basis. For example, data may be received from a system bus at a faster rate than the data can be properly handled by the destination circuitry. To avoid any problems that might be caused by this difference in data rates, the receiver circuit can store the data in a FIFO at a first clock rate (e.g., a write clock rate compatible with the system bus), and retrieve the data at a second clock rate (e.g., a read clock rate compatible with the destination circuitry).
A FIFO can have a maximum width and a maximum depth. For example, a FIFO might have a maximum width of 36 bits and a maximum depth of 4 k (4098) words. To increase the width of a memory circuit (e.g., the number of bits in a word) by using multiple FIFOs is relatively straightforward. For example, to store values of up to 72 bits, two FIFOs with a maximum width of 36 bits can be used, with the more significant 36 bits being stored in the first FIFO, and the less significant 36 bits being stored in the second FIFO.
FIG. 1 shows one known method of concatenating FIFOs to increase the overall depth of the memory circuit (e.g., the number of words that can be stored in the memory circuit). In the memory circuit of FIG. 1, four FIFOs 101-104 are concatenated in series. The same method can also be applied to fewer or more than four FIFOs. A first FIFO 101 has an input port coupled to a write interface 111 of the memory circuit. The last FIFO 104 in the series has an output port coupled to a read interface 112 of the memory circuit. In the pictured memory circuit, the first two FIFOs 101, 102 are operated in the write clock domain (e.g., using write clock signal WR_CLK), and the last FIFO 104 is operated in the read clock domain (e.g., using read clock signal RD_CLK). As shown by dotted line 121, the third FIFO 103 in the series is operated partially in the write clock domain and partially in the read clock domain, with write cycles being controlled by signal WR_CLK and read cycles being controlled by signal RD_CLK. Note that the transition between clock domains can occur in any of the four FIFOs. The location for the transition is typically determined based on the relative clock rates of the write and read clocks. It is generally desirable to operate most of the FIFOs in the faster of the two clock domains, to avoid bottlenecks in writing and reading data.
The memory circuit of FIG. 1 has some disadvantages. For example, the write-to-read latency (the number of clock cycles required for a word written to an empty memory circuit to be available for reading) can be unacceptably long for some applications. For highly parameterizable applications, e.g., where the number of FIFOs being concatenated can vary, the write-to-read latency may also vary, which can be undesirable. Further, when there is a significant difference in frequency between the write clock and the read clock, data bottlenecks can occur, which can cause unpredictable status flag behavior. Therefore, the memory circuit of FIG. 1 might not be suitable for some applications in which the write and read clocks are asynchronous and/or the clock frequencies are not stable or are not well-characterized.
Therefore, it is desirable to provide memory circuits that are more suitable for asynchronous applications than the memory circuit illustrated in FIG. 1.